Knowledge

In the world of electronics design, high-performance design has its own unique challenges.

1 The birth of high-speed design

In recent years, the increasing number of high-frequency signal designs has been closely linked to the steadily increasing performance of electronic systems.

As system performance improves, the challenges for PCB designers are increasing day by day: smaller chips, denser circuit board layout, and lower power consumption chip requirements.

With the rapid development of all technologies, we are at the core of high-speed design and need to consider its complexity and all factors.

2 review

PCB design has changed a lot over the past 30 years. In 1987, we thought 0.5 micron was the end of the technology, but today, 22nm has become the norm.

As shown in the figure below, the edge rate in 1985 promoted the increase in design complexity (typically 30 nanoseconds), and today the edge rate has become 1 nanosecond.

Changes in marginal rates over the past 30 years.

3 Technological progress is accompanied by various problems

The advancement of technology is always accompanied by a series of problems. As system performance increases and high-speed designs are adopted, some issues must be addressed in the design environment.

Below, we summarize the challenges faced:

Signal quality

IC manufacturers favor lower core voltages and higher operating frequencies, which results in sharply rising edge rates. Edge rates in unterminated designs will cause reflections and signal quality issues.

crosstalk

In high-speed signal designs, dense paths often lead to crosstalk—the phenomenon associated with electromagnetic coupling between traces on a PCB.

Crosstalk can be edge coupling of traces on the same layer or broadside coupling on adjacent layers.

The coupling is three-dimensional. Parallel paths and wide-side traces cause more crosstalk than side-by-side trace paths.

Broadside coupling (top) compared to edge coupling (bottom)

Fast edge rates in traditional designs can cause ringing on unterminated transmission lines, even when using the same frequency and trace length as before.

This essentially results in higher emissions, well in excess of the FCC/CISPR Class B limits for unterminated transmission lines.

Edge rate radiation at 10 nanoseconds (left) and 1 nanosecond (right).

4 Design Solutions

Signal and power integrity issues occur intermittently and are difficult to diagnose. Therefore, the best way is to find the root cause of the problem during the design process and eliminate it, rather than trying to solve it in the later stages and delaying production.

The stackup planning tool makes it easier to implement solutions to signal integrity issues in your design.

5 Circuit board stackup planning

The number one priority in high-speed design must be circuit board stackup. The substrate is the most important component of the assembly, and its specifications must be carefully planned to avoid discontinuous impedance, signal coupling, and excessive electromagnetic radiation.

When looking at the circuit board stackup for your next design, keep these tips and suggestions in mind:
All signal layers need to be adjacent and tightly coupled to an uninterrupted reference plane that creates a clear loop and eliminates broadside crosstalk.

The substrate of each signal layer is adjacent to the reference plane.

There are good planar capacitors to reduce AC impedance in high frequencies. The tightly coupled inner electrical layer plane reduces the AC impedance of the top layer and greatly reduces electromagnetic radiation.

Reducing the dielectric height significantly reduces crosstalk without impacting the available space on the board.

The substrate should be able to accommodate a range of different technologies. For example: 50/100 ohm digital, 40/80 ohm DDR4, 90 ohm USB.

6 Cabling and Workflow

With your stackup carefully planned, the next step is to focus on board routing. Based on design rules and careful configuration of your work area, you can route your board most efficiently and successfully.

These tips can help make your wiring easier and avoid unnecessary crosstalk, radiation, and signal quality problems:

Simplify the view to clearly see the split planes and current loops.

To do this, first determine which copper foil plane (ground or power) serves as the reference plane for each signal layer, and then open the signal layer and internal electrical layer planes to view them at the same time. This helps you more easily see the traces that split the plane.

Multiple signal layers (left), top and adjacent plane views (right)

If a digital signal must cross a power reference plane, you can place one or two decoupling capacitors (100nF) close to the signal. This provides a current loop between the two power supplies.

Avoid parallel routing and broadside routing, which can cause more crosstalk than side-by-side routing.

Unless you are using a synchronous bus, keep the parallel intervals as short as possible to reduce crosstalk. Leave room for signal groups so that their address and data spacing is three times the trace width.

Be careful when using combined microstrip layers on the top and bottom layers of the board. This can lead to crosstalk between traces on adjacent board layers, compromising signal integrity.

Routing the clock (or strobe) signal with the longest delay by signal group ensures that the data has been established before the clock is read.

Routing embedded signals between planes helps minimize radiation and provides ESD protection.

7 Signal clarity

In the future, the complexity of electronic design will undoubtedly continue to increase, which will bring a series of challenges to PCB designers that need to be solved. Ensuring the correct configuration of circuit board stackup, impedance, and current loops is the basis for design stability.