Knowledge

Via  is one of the important components of multi-layer PCB, and the cost of drilling usually accounts for 30% to 40% of the PCB board manufacturing cost. Simply put, every hole on the PCB can be called a via. From a functional point of view, vias can be divided into two categories: one is used for electrical connections between layers; the other is used for fixing or positioning devices. From a process perspective, these vias are generally divided into three categories, namely blind vias, buried vias and through vias. Blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface circuits and the inner circuits below. The depth of the holes usually does not exceed a certain ratio (aperture). Buried vias refer to connection holes located on the inner layer of a printed circuit board and do not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board. They are completed using the through-hole forming process before lamination. During the via-hole formation process, several inner layers may be overlapped.

The third type is called a through hole, which passes through the entire circuit board and can be used to implement internal interconnections or as mounting positioning holes for components. Because through holes are easier to implement in technology and have lower costs, most printed circuit boards use them instead of the other two via holes. The following via holes are considered as through holes unless otherwise specified.

From a design point of view, a via hole mainly consists of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via. Obviously, when designing high-speed, high-density PCBs, designers always hope that the via holes should be as small as possible, so that more wiring space can be left on the board. In addition, the smaller the via holes, the smaller their own parasitic capacitance will be. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction in hole size also brings about an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by process technologies such as drilling (drill) and electroplating (plating): the smaller the hole, the harder it is to drill. The longer the hole takes, the easier it is to deviate from the center; and when the depth of the hole exceeds 6 times the drill diameter, there is no guarantee that the hole wall will be evenly plated with copper. For example, if the thickness (through hole depth) of a normal 6-layer PCB board is 50 Mil, then under general conditions, the drilling diameter that the PCB manufacturer can provide can only reach 8 Mil. With the development of laser drilling technology, the size of drilled holes can also become smaller and smaller. Generally, vias with a diameter of less than or equal to 6 Mils are called microvias. Microvias are often used in HDI (High Density Interconnect Structure) design. Microvia technology allows vias to be drilled directly on the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.

Vias appear as discontinuous impedance breakpoints on the transmission line, which will cause signal reflection. Generally, the equivalent impedance of a via hole is about 12% lower than that of a transmission line. For example, the impedance of a 50-ohm transmission line will be reduced by 6 ohms when passing through the via hole (specifically, it is related to the size of the via hole and the thickness of the board, not reduction). However, the reflection caused by the discontinuous impedance of the via is actually minimal. The reflection coefficient is only: (44-50)/(44+50)=0.06. The problems caused by the via are more concentrated on the parasitic capacitance and inductance. Impact.

2. Parasitic capacitance and inductance of vias

The via itself has parasitic stray capacitance. If it is known that the diameter of the solder mask area of the via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50 Mil, if the diameter of the via pad used is 20 Mil (the drilling diameter is 10 Mils) and the diameter of the solder mask area is 40 Mil, then we can approximately calculate the through hole through the above formula The parasitic capacitance is roughly: C=1.41×4.4×0.050×0.020/(0.040-0.020)=0.31pF. The change in rise time caused by this part of the capacitance is roughly: T10-90=2.2C(Z0/2)=2.2×0 .31x(50/2)=17.05ps

It can be seen from these values that although the effect of slowing down the rise delay caused by the parasitic capacitance of a single via is not very obvious, if vias are used multiple times in the wiring for switching between layers, multiple vias will be used , should be carefully considered when designing. In actual design, parasitic capacitance can be reduced by increasing the distance between vias and copper areas (Anti-pad) or reducing the diameter of the pad.

There are parasitic capacitances and parasitic inductances in vias. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following empirical formula to simply calculate the approximate parasitic inductance of a via: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is The diameter of the center drill hole. It can be seen from the formula that the diameter of the via hole has a small impact on the inductance, but the length of the via hole affects the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance size It is: XL=πL/T10-90=3.19Ω. Such impedance cannot be ignored when high-frequency current flows through it. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the vias will increase exponentially.

3. How to use vias

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, try to do the following in the design:

1. Consider both cost and signal quality, and choose a reasonably sized via size. If necessary, you can consider using different sizes of vias. For example, for power or ground vias, you can consider using larger sizes to reduce impedance, while for signal traces, you can use smaller vias. Of course, as the via size decreases, the corresponding cost will also increase.

2. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reducing the two parasitic parameters of the via.

3. Try not to change layers of signal traces on the PCB board, which means try not to use unnecessary vias.

4. The power and ground pins should be drilled nearby, and the leads between the vias and the pins should be as short as possible. You can consider drilling multiple vias in parallel to reduce the equivalent inductance.

5. Place some grounded vias near the vias of the signal layer to provide a close return path for the signal. You can even put some extra ground vias on the PCB board.

6． For higher-density, high-speed PCB boards, consider using micro vias.
​