Knowledge

We know that when designing circuits, in order to improve the performance of the product, we must take into account the electromagnetic interference it receives. There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coatings, selecting appropriate EMI suppression components and EMI simulation design, etc. This article starts from the most basic PCB layout and discusses the role and design techniques of PCB layer stacking in controlling EMI radiation.

Power bus

Reasonably placing a capacitor of appropriate capacity near the IC’s power pin can make the IC’s output voltage jump faster. However, the problem does not end there. Due to the finite frequency response of the capacitor, the capacitor cannot generate the harmonic power required to cleanly drive the IC output over the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop across the inductor of the decoupling path. These transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

In the case of ICs on our circuit boards, the power plane around the IC can be thought of as a good high-frequency capacitor, which collects the energy leaked from the discrete capacitors that provide high-frequency energy for a clean output. In addition, the inductance of a good power supply layer should be small, so the transient signal synthesized by the inductor should also be small, thereby reducing common-mode EMI.

Of course, the connection from the power layer to the IC power pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster. It is best to connect it directly to the pad where the IC power pin is located, which needs to be discussed separately.

To control common-mode EMI, the power plane must aid in decoupling and have sufficiently low inductance. This power plane must be paired with a reasonably well-designed power plane. Some may ask, how good is good? The answer to the question depends on the layering of the power supply, the materials between the layers, and the operating frequency (i.e., a function of the IC rise time). Typically, the spacing between power layers is 6mil, and the interlayer is made of FR4 material, so the equivalent capacitance of the power layer per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

There are not many devices with a rise time of 100 to 300ps, but according to the current IC development speed, devices with a rise time in the range of 100 to 300ps will account for a high proportion. For circuits with 100 to 300ps rise time, 3mil layer spacing will no longer be suitable for most applications. At that time, it will be necessary to use layering technology with layer spacing of less than 1 mil and replace the FR4 dielectric material with a material with a very high dielectric constant. Today, ceramics and ceramic-coated plastics can meet the design requirements of circuits with rise times from 100 to 300ps.

Although new materials and approaches may be adopted in the future, for today’s common 1 to 3ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, it is usually sufficient to handle the high end harmonics and keep the transients low enough, that is , common mode EMI can be reduced very low. The PCB layer stackup design examples given in this article will assume a layer spacing of 3 to 6 mils.

Electromagnetic shielding

From the perspective of signal routing, a good layering strategy should be to place all signal routing on one or several layers, with these layers next to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer is as small as possible. This is what we call the “layering” strategy.

PCB stacking

What kind of stacking strategy helps shield and suppress EMI? The following layered stacking scheme assumes that the supply current flows on a single layer and that single or multiple voltages are distributed on different parts of the same layer. The case of multiple power planes is discussed later.

4 layers board

There are several potential problems with the 4-layer board design. First of all, for a traditional four-layer board with a thickness of 62 mil, even if the signal layer is on the outer layer and the power and ground layers are on the inner layer, the distance between the power layer and the ground layer is still too large.

If cost requirements are the first priority, you can consider the following two alternatives to traditional 4-layer boards. Both solutions can improve the performance of EMI suppression, but are only suitable when the component density on the board is low enough and there is sufficient area around the components to place the required power copper layer.

The first is the preferred solution. The outer layers of the PCB are both ground layers, and the two middle layers are signal/power layers. The power supply on the signal layer is routed with wide traces, which allows the supply current to have a low impedance path and the signal microstrip path to have a low impedance. From an EMI control perspective, this is the best 4-layer PCB structure available. In the second solution, the outer layer carries power and ground, and the middle two layers carry signals. Compared with the traditional 4-layer board, this solution has smaller improvements, and the interlayer impedance is as poor as the traditional 4-layer board.

If you want to control the trace impedance, the above stacking scheme must be very careful to arrange the traces under the power and ground copper islands. In addition, copper islands on power or ground planes should be interconnected as much as possible to ensure DC and low-frequency connectivity.

6-layer board

If the density of components on a 4-layer board is relatively high, it is best to use a 6-layer board. However, some stacking schemes in the 6-layer board design do not shield the electromagnetic field well enough, and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.

In the first example, the power supply and ground are placed on the 2nd and 5th layers respectively. Since the copper impedance of the power supply is high, it is very unfavorable for controlling common mode EMI radiation. However, from the perspective of signal impedance control, this method is very correct.